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Espressif Systems /ESP32-C6 /EXTMEM /L1_ICACHE0_PRELOAD_CTRL

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Interpret as L1_ICACHE0_PRELOAD_CTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (L1_ICACHE0_PRELOAD_ENA)L1_ICACHE0_PRELOAD_ENA 0 (L1_ICACHE0_PRELOAD_DONE)L1_ICACHE0_PRELOAD_DONE 0 (L1_ICACHE0_PRELOAD_ORDER)L1_ICACHE0_PRELOAD_ORDER 0L1_ICACHE0_PRELOAD_RGID

Description

L1 instruction Cache 0 preload-operation control register

Fields

L1_ICACHE0_PRELOAD_ENA

The bit is used to enable preload operation on L1-ICache0. It will be cleared by hardware automatically after preload operation is done.
L1_ICACHE0_PRELOAD_DONE

The bit is used to indicate whether preload operation is finished or not. 0: not finished. 1: finished.
L1_ICACHE0_PRELOAD_ORDER

The bit is used to configure the direction of preload operation. 0: ascending, 1: descending.
L1_ICACHE0_PRELOAD_RGID

The bit is used to set the gid of l1 icache0 preload.

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data